PICMG, a leading consortium for the development of open embedded computing specifications, announces that the MicroTCA Working Group is working on the next generation of the MTCA architecture specifications initially launched in 2006. Efforts target improvements for time sensitive and high bandwidth applications such as in high-energy physics. Current work includes accommodations for the next generation of CPUs and FPGAs that will natively support PCIe gen 5. Future applications in industry require this higher bandwidth i.e. for image processing, signal detection, data acquisition. As current CPU speeds are limited by 80 W per slot power limit the support of more power for faster CPUs is on the task list as well. Future applications will also require other kinds of high- and low-speed fabrics paired with more flexibility in system design. The science market segment for high frame rate Megapixel detectors of the actual photon experiments requires even higher throughput. Thus, all these demands are scheduled to become part of the new releases of these successful specifications. With all these improvements MicroTCA continues to be an pro-active specification with significant updates to support high-bandwidth backplane interconnects. Latest update of the specs happened as recently as 2020.
“I am more than happy that the MicroTCA Working Group is so pro-actively addressing the recent demands. The new spec will find its way into many different vertical markets due to the flexibility of MicroTCA!”, says Heiko Koerte, VP and Director Sales & Marketing of N.A.T., “Applications in industrial automation, medical, telecommunication and networking, aerospace and transportation will not only benefit from these new features but also from how easily MicroTCA can be adapted to the exact needs. More than 16.500 MCHs just from N.A.T and many more I/O and compute cards delivered to the field speak for themselves. The wide spread of MicroTCA definitely makes it both a technically and commercially attractive solution!”.
MicroTCA® is a modular, open standard for building high-performance, backplane-based switched fabric computer systems in a small form factor.
MicroTCA has become the de facto standard for precision timing and synchronization equipment at world-renowned particle accelerators CERN, DESY, ESS, XFEL, KEK, SLAC, and others. Its architecture and features are also consistent with the Modular Open Systems Approach (MOSA) being adopted as part of the U.S. Department of Defense (DoD) electronic media acquisition policy.
Originally designed for edge telecom and networking use cases, the core MTCA.0 base specification defines the mechanical and electrical characteristics of a MicroTCA backplane, card cage, power subsystem, cooling, and system management. Since being ratified in 2011, the MTCA Base specification has been revised to support 10GBASE-KR and 40GBASE-KR4 Ethernet fabrics and spawned four additional sub-specifications adapted for data acquisition, control, and telemetry in markets such as high-energy physics, avionics, defense, mobile infrastructure, and others.
- 0 – The Base specification defines MicroTCA’s electrical, mechanical, thermal, and management characteristics, including support for implemented in MicroTCA.0 Revision 2.0 in 2020.
- 1 – Adds ruggedization features and forced-air cooling.
- 2 –Expands shock, vibration, and temperature operation, allowing for both air and conduction cooling.
- 3 – Continues to increase compliance threshold for shock, vibration, and temperature and requires the use of conduction cooling.
- 4 – Adds features for the scientific community such as Rear Transition Modules (RTMs), which improve RF filtering, pre- and post-processing, clock generation, etc.
Developed as a reduced-footprint alternative to the popular AdvancedTCA family of specifications, MicroTCA defines a backplane-based system for plug-in Advanced Mezzanine Cards (AdvancedMCs). AdvancedMCs are available in different sizes (Full-size, Mid-size, Compact) and can be sourced from multiple vendors to add compute, storage, I/O, and other functionality to a MicroTCA chassis without modification. As mentioned previously, the MTCA.4 sub-specification also adds support for RTMs that increase system expansion possibilities in scientific applications.
A single MicroTCA system contains up to 12 AdvancedMCs slots, and up to two MicroTCA Carrier Hubs (MCHs). MCHs provide intelligent platform management, power delivery, and facilitate switching over Ethernet, PCIe, and/or Serial RapidIO backplane interconnect fabrics.
To learn more about the PICMG MicroTCA family of specifications, download the Short Form Specification for free at https://www.picmg.org/wp-content/uploads/MicroTCA_Short_Form_Sept_2006.pdf. You can also purchase Revision 2.0 of the MicroTCA Base Specification for $750 from https://www.picmg.org/product/microtca-base-specification-r2-0.
The current committee is led by Kay Rehlich of DESY, Heiko Koerte of N.A.T. and Thomas Holzapfel from powerBridge.
Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organizations that collaboratively develop open standards for high performance industrial, Industrial IoT, military & aerospace, telecommunications, test & measurement, medical, and general-purpose embedded computing applications. There are over 130 member companies that specialize in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signaling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.
Key standards families developed by PICMG include COM Express, COM-HPC, ModBlox7, IoT.1, CompactPCI, AdvancedTCA, MicroTCA, AdvancedMC, CompactPCI Serial, COM Express, SHB Express, MicroSAM, and HPM (Hardware Platform Management). https://www.picmg.org